verilog - What are the uses of force - release statements? -

from hardware point of view, force - release statements model? uses of force - release statement?

the force/release statements used aid in simulations.

one scenario avoid x-propagation in gate simulations. rtl code contains registers without asynchronous resets. although rtl simulations run cleanly, gate simulations not. either x's never resolved, or take many cycles resolve make simulations take impractical amount of time run. forcing , releasing random known value register during reset, simulation allowed proceed cleanly , complete in timely manner.

another scenario involves large counters. example, see 32-bit counter roll over, requires 4 billion cycles. typically, want roll on several times in 1 simulation. again, take impractically long time simulate. force/release can used deposit random value counter close roll-over value.

another scenario involves boosting code coverage results. can difficult achieve 100% coverage on metrics, when using ip can not modified. force can used toggle unused signal.

the force/release should used sparingly , when convinced valid so.