vhdl - Xilinx / ISim seem claims value to be X but it has been declared -

have started learning how use tool if question seems silly apologize in advance. have searched error in numerous forums (already answered posts , not mine) , couldn't understand doing wrong here question:

my behavioral code:

-----------------------------------------------------------------------------    ----- -- company:  -- engineer:  --  -- create date:    01:47:22 07/07/2015  -- design name:  -- module name:    module_1 - behavioral  -- project name:  -- target devices:  -- tool versions:  -- description:  -- -- dependencies:  -- -- revision:  -- revision 0.01 - file created -- additional comments:  -- -----------------------------------------------------------------------------    ----- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all;   -- uncomment following library declaration if using -- arithmetic functions signed or unsigned valuessss --use ieee.numeric_std.all;  -- uncomment following library declaration if instantiating -- xilinx primitives in code. --library unisim; --use unisim.vcomponents.all;  entity module_1     port (a,b,we,reset : in std_logic;             clk : in std_logic;             din : in signed(3 downto 0);             full,empty,error : out std_logic:= '0';             parkfree : out signed(3 downto 0)             ); end module_1;  architecture behavioral of module_1 signal current_state,next_state:std_ulogic_vector(1 downto 0);     signal empty_bf, full_bf :std_ulogic;     signal enter, reset_b : std_ulogic := '0' ;     constant s0: std_ulogic_vector (1 downto 0):="00"; constant s1: std_ulogic_vector (1 downto 0):="10"; constant s2: std_ulogic_vector (1 downto 0):="11"; constant s3: std_ulogic_vector (1 downto 0):="01"; signal  park_counter,buffr: signed(3 downto 0):="0000"; signal parktotal,free_park_counter: signed(3 downto 0):= "1111"; begin   p1: process (clk,reset,reset_b) begin        if (reset = '1')     current_state <= s0;   elsif clk'event , clk = '1'     current_state <= next_state; end if; end process p1;  p2: process (current_state,a,b) begin next_state <= current_state;  case current_state     when s0 =>         if = '1'             enter <= '1';             next_state <= s1;         elsif b = '1'             next_state <= s3;         end if;      when s1 =>             if = '0'                 enter <= '0';                 next_state <= s0;             elsif b = '1'                 next_state <= s2;             end if;       when s2 =>             if = '0'                 next_state <= s3;             elsif b = '0'                 next_state <= s1;             end if;      when s3 =>          if b = '0'             enter <= '0';             next_state <= s0;         elsif = '1'             next_state <= s2;         end if;      when others =>      end case; end process p2;   p3: process(current_state,a,b) begin  case current_state     when s1 =>         if enter = '0' , = '0' , empty_bf = '0'             park_counter <= park_counter - 1;             free_park_counter <= free_park_counter + 1;             error <= '0';         end if;      when s3 =>         if enter = '1' , b = '0' , full_bf = '0'             park_counter <= park_counter + 1;             free_park_counter <= free_park_counter - 1;             error <= '0';         end if;      when others =>      end case; end process p3;  max: process(we) begin  if clk'event , clk = '1' , = '1'     parktotal <= din ;     buffr <= din ;     if (free_park_counter < buffr - park_counter)         error <= '1';         reset_b <= '1';     else    free_park_counter <=  buffr - park_counter;     end if; end if;  end process max;  incr: process(free_park_counter,din) begin parkfree <= free_park_counter; if (free_park_counter = 15)     empty <= '1';     empty_bf <= '1'; else    empty <= '0';         empty_bf <= '0'; end if; if (free_park_counter = 0)     full <= '1';     full_bf <= '1'; else    full <= '0';         full_bf <= '0'; end if;  end process incr;        end behavioral; 

my testbench

-----------------------------------------------------------------------------    --- -- company:  -- engineer: -- -- create date:   02:17:07 07/11/2015 -- design name:    -- module name:   d:/users/ergasiafpga/testbench.vhd -- project name:  ergasiafpga -- target device:   -- tool versions:   -- description:    --  -- vhdl test bench created ise module: module_1 --  -- dependencies: --  -- revision: -- revision 0.01 - file created -- additional comments: -- -- notes:  -- testbench has been automatically generated using types std_logic , -- std_logic_vector ports of unit under test.  xilinx recommends -- these types used top-level i/o of design in order -- guarantee testbench bind correctly post-implementation  -- simulation model. -------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all;  -- uncomment following library declaration if using -- arithmetic functions signed or unsigned values --use ieee.numeric_std.all;  entity testbench end testbench;  architecture behavior of testbench   -- component declaration unit under test (uut)  component module_1 port(      : in  std_logic;      b : in  std_logic;      : in  std_logic;      reset : in  std_logic;      clk : in  std_logic;      din : in  signed(3 downto 0);      full : out  std_logic;      empty : out  std_logic;      error : out  std_logic;      parkfree : out  signed(3 downto 0)     ); end component;      --inputs    signal : std_logic := '0';    signal b : std_logic := '0';    signal : std_logic := '0';    signal reset : std_logic := '0';    signal clk : std_logic := '0';    signal din : signed(3 downto 0) := (others => '0');  --outputs    signal full : std_logic;    signal empty : std_logic;    signal error : std_logic;    signal parkfree : signed(3 downto 0);     -- clock period definitions    constant clk_period : time := 10 ns;  begin  -- instantiate unit under test (uut)    uut: module_1 port map (       => a,       b => b,       => we,       reset => reset,       clk => clk,       din => din,       full => full,       empty => empty,       error => error,       parkfree => parkfree     );     -- clock process definitions    clk_process :process    begin     clk <= '0';     wait clk_period/2;     clk <= '1';     wait clk_period/2;    end process;      -- stimulus process    stim_proc: process    begin               -- hold reset state 100 ns.     reset <= '1' ;   wait 100 ns;       reset <= '0' ;   wait clk_period*10;    -- insert stimulus here      <= '1' ;     wait clk_period*5;     b <= '1' ;     wait clk_period*5;     <= '0' ;     wait clk_period*5;     b <= '0' ;     wait clk_period*5;     b <= '1' ;     wait clk_period*5;     <= '1' ;     wait clk_period*5;     b <= '0' ;     wait clk_period*5;     <= '0' ;   wait;    end process;  end; 

i posted whole code in case i'm missing in part of wouldn't think about. , when isim , "succesful" trigger of p3...

referencing again here:

p3: process(current_state,a,b) begin  case current_state     when s1 =>         if enter = '0' , = '0' , empty_bf = '0'             park_counter <= park_counter - 1;             free_park_counter <= free_park_counter + 1;             error <= '0';         end if;      when s3 =>         if enter = '1' , b = '0' , full_bf = '0'             park_counter <= park_counter + 1;             free_park_counter <= free_park_counter - 1;             error <= '0';         end if;      when others =>      end case; end process p3; 

...the isim says in part

"there 'u'|'x'|'w'|'z'|'-' in arithmetic operand, result 'x'(es)."

and proceeds make xs of of values after part , although of signals have been initialized (at least ones in part)

the "park_counter <= park_counter + 1;" part works correctly in simulation "free_park_counter <= free_park_counter -1;" doesn't. baffles me declared same type , both initialized same way , different values.

so missing or doing blatantly wrong? incredibly appreciated. looking error , if please contain optimizations since i'm looking learn through trial , error , thought , struggle make better myself

in addition , please patient responses since log on 2 3 times per day. in advance

your design non-workable per brian's answer. testbench causes messages when going s3 or s1 s0 before clock edge. free_park_counter goes 'u's. (once gets u's won't loop further, no events occur without signal value change).

your counters should clocked prevent combinatorial looping, plus won't synthesize clock usefully due uneven combinatorial delays. sensitivity lists should likewise complete, if no other reason intent make simulation match synthesized result.

looking @ result of testbench:

(clickable)

we can compare messages arithmetic operators found in synopsys package std_logic_arith:

../../../src/synopsys/std_logic_arith.vhdl:315:20:@350ns:(assertion warning): there 'u'|'x'|'w'|'z'|'-' in arithmetic operand, result 'x'(es).
../../../src/synopsys/std_logic_arith.vhdl:315:20:@350ns:(assertion warning): there 'u'|'x'|'w'|'z'|'-' in arithmetic operand, result 'x'(es).
../../../src/synopsys/std_logic_arith.vhdl:315:20:@550ns:(assertion warning): there 'u'|'x'|'w'|'z'|'-' in arithmetic operand, result 'x'(es).

the signals displayed in waveform selected in order of importance , appearance first pass selection , see 'u's on free_park_counter error.

error catches attention because hadn't mentioned previously. when asking 'where 'u' come ?' becomes apparent issue there drivers on error , free_park_counter in both processes p3 , max. messages side effect.

each process assigning signal provides driver. signals multiple drivers either resolved or result in error non-resolved types.

the resolved value of free_park_counter 1 or more elements having metavalue cause diagnostic messages produced package std_logic_arith. 'u's in waveform caused resolution of 2 drivers.

the difficulty audience had in noticing 2 drivers may in part due strong insistence on focusing on process p3, not specified. title , focus of question seems bit unclear. without minimal complete , verifiable example there bound less scrutiny.

you might expect minimum consolidate assignments error , free_park_counter single process. error should registered, , i'd expect named park_counter want registered, too.